Electronic chip designers use a variety of computer-aided design tools. After creating a register-transfer level design they typically use a static timing analysis tool to check for timing issues. The static timing analysis tool can predict setup and hold violations, give a performance estimates and indicate other timing issues. The static timing analysis tool requires the user to supply clock timing information. Chip designers typically specify the clock timing information in a format such as the Synopsys Design Constraint (SDC) language. If a user makes a mistake in the clock timing information the final chip may not work.
Modern electronic chip designers usually try to minimize the power requirement of the chips they develop. Designs contain many registers and each register value transition consumes power. Designers try to reduce the power consumption by reducing the frequency of register transitions. Power saving techniques include: a) running parts of the design at a lower clock frequencies; b) dynamically disabling the clock to a part of the design when the associated function is not required; and c) dynamically switching between clocks of different frequency. The design will typically contain one or more master clocks and multiple lower-frequency generated-clocks derived from the master clocks.
Atrenta's Spyglass Clk_Gen23 rule, as described in its Spyglass User Guide, checks structurally whether generated-clocks have been defined correctly and reports some incorrectly defined generated-clocks. It looks for specific components connected in specific ways. Since it performs structural checks it can handle only a limited number of logic structures. It is impossible to verify all forms of generated-clocks structurally as the involved logic can be complex and can have many different patterns. For example, a simple divide_by—2 generated-clock can be generated in many ways.